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1:0321 1:0351 Negative Voltage Hot Swap Controller with Active Power Filter Features
Live Insertion and Removal Power Manager Adjustable Power-on slew rate Autodetect of Load Open Circuit or -VIN Disconnection Controlled Time-Delay Operates from 9 V to External MOSFET Voltage Limit Fault Indication Output (microprocessor reset). Board Insertion/Removal Detector Input Protection During Turn-On Low frequency Power Active Filter Adjustable Electronic Circuit Breaker Vin undervoltage with GSNSin input
Description
The IXHQ100 is a live insertion and removal hot swap controller with a built-in power noise filter. It incorporates all the active circuitry necessary to protect circuit boards during live insertion or removal (insertion or removal when the system power is active). Additionally, the IXHQ100 incorporates two unique features: power active filter for powerline noise suppression and power auto-disconnect detector which eliminates the need of additional staggered pins. The IXHQ100 shunt regulator ensures a wide operating voltage range (with the external MOSFET breakdown voltage as limit). The active power filter reduces power source output impedance, producing "clean" load power. The IXHQ100 allows continuous load current rise adjustments, presettable maximum current limits, and user selectable fault indication turn off times for resetting Ps and other synchronous board level systems. For added flexibility, GSNSin pin is available to implement either circuit board insertion/removal detection or ground detection. US Patents Pending.
Applications
Arcless card insertion and removal Central Office Switching Hardware Circuit Boards From -48 V Distributed Power Supplies Circuit Board Power Manager and Noise Filter Circuit Board Hot Swap Protector and Manager Electronic Circuit Breaker Wireless Local Loop Antennas Cable TV Antenna
Typical Application with Auto-Disconnect Detector
CAUTION: These devices are sensitvie to electrostatic discharge; take caution when handling and assembling this component.
Figure 1
IXYS reserves the right to change limits, test conditions and dimensions.
Copyright (c) IXYS CORPORATION 2000
www.ixys.com 1
98716 (08/14/00)
IXHQ 100PI IXHQ 100SI Absolute Maximum Ratings
Symbol VCC-VAGND Definition Voltage applied VCCin to AGND Shunt On: Shunt On for 10 seconds All other pins except VDC VDD Load Current Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Supply Current with Shunt On Max. Rating Shunt Off: -0.3 V to 16 V -0.3 V to 14 V 14V to 16 V -0.3 V to VCCin + 0.3 V 60 mA 125 oC -40 oC to 85 oC -40 oC to 150 oC 25 mA
Pin Description
IVDD TJM TJ0 Tstg IDD
Electrical Characteristics
Unless otherwise noted, TA = 25 oC; -VIN= 48 V, AGND connected to -VIN, VSHUNToff = 5 V, VCC = 12 V, VGSNSin= 12 V. All voltage measurements with respect to AGND. IXHQ100 configured as described in Test Conditions.
Symbol ICC VCCSHUNT VTHSHUNToff ISHUNToff VTHINV RINV VTHGSNS IGSNSin ICAPin VVDROP RVDROP ISLOPE RSLOPEDCHG IOFFTM ROFFTMCHG VTHOFFTM VCL
Parameter Supply current VCC shunt regulation voltage SHUNToff input threshold voltage SHUNToff input bias current INV input threshold voltage INV input resistance GSNS sense input threshold voltage GSNSin input bias current CAPin input bias current Active filter offset voltage VDROP input resistance SLOPE capacitor charging current SLOPE capacitor discharge resistance OFFTM capacitor charging current OFFTM capacitor discharge resistance OFFTM input threshold voltage
Test Conditions VCC=12 V, VSHUNToff = VCC, all outputs unloaded. ICC forced to 10 mA when shunt is off VCC = 15 V, monitor RSTOUT
Min
Typ 2
Max Units 3 16 2 1 10 180 6 -2 1 1.1 90 110 200 120 200 5.5 mA V V A V K V A A V K mA mA V
12 1 -1
13.8 1.5 0 8 130 5.8 -2.3 0 0.9 70 85 90
VCC = 12 V, monitor RSTOUT
6 70
VCC = 12 V, monitor RSTOUT
4.5 -2.6 -1 0.7 50
VOFFTM = 5 V, VGSOURCE = 0 V VCAPin= 5 V VDROP = 5 V, IVT = VCC VSOURCE = 0 V, VCAPin= 5 V VDROP = 5 V, VSOURCE = 0 V VCAPin= 5 V
70
80
100 111
OFFTM input voltage when SLOPE input voltage starts its ramp
3.8
4.5
Overcurrent threshold bias voltage
2
90
125
150
mV
IXHQ 100PI IXHQ 100SI
Electrical Characteristics (continued)
Symbol RVCL tOC dvGATE/dt VGATE IGATE IGATE VDD IRSTout tRST Vad Parameter VCL bias resistance Overcurrent detection to GATE output delay GATE output slew rate Maximum GATE output voltage GATE pull-up current GATE pull-down current VDD regulator output Voltage RSTout drive current RST pulse width Auto-Detect threshold Gate drive on; ramp VOUTsns; monitor RST until it pulses. VCAPin = 0 V; VOUTsns = 5 V VSOURCE input is a step at t = 0s from 0 V to 200 mV CSLOPE= 100 nF VCAPin = 0 V; R = 10 K load VOUTsns = 5 V Gate drive on, VGATE = 0 V Gate drive off VGATE = 10 V 3.3K Resistive load between VDD output and AGND Force VRSTout =1 V during fault condition 10 5 2.4 200 -10 Test Conditions Min 4 Typ 6 20 Max Units 10 30 k ms
0.5
0.8 13.8 -15 20 5.75 3 500 12
1.1 V/ms 15 -10 V mA mA 6.5 3.6 1000 20 V mA ns mV
Note 1: Operating the device beyond parameters with listed "absolute maximum ratings" may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note2: All voltages are relative to ground unless otherwise specified.
Typical Performance Characteristics
Graph 1: Icc vs. Temperature
2.18 2.16 2.14 2.12
Graph 2: Regulator Output Voltage vs. Temperature
6.0
Regulator Output Voltage (V)
-40 -20 0 20 40 60 80 100
5.9 5.8 5.7 5.6 5.5 5.4 -60 -40 -20
Icc (mA)
2.10 2.08 2.06 2.04 2.02 2.00 1.98 1.96 -60
Temperature (oC)
0
20 40 60 80 100
Temperature (oC)
3
IXHQ 100PI IXHQ 100SI
Graph 3: SLOPE Pin current vs. Temperature
94 92 90
Graph 4: OFFTM Threshold Voltage vs. Temperature
6
OFFTM Threshold Voltage (V)
Slope Current (uA)
88 86 84 82 80 78 76 -60 -40 -20 0 20 40 60 80 100
5
4
Temperature (oC)
3 -60
-40
-20
Temperature (oC)
0
20
40
60
80
100
Graph 5: Vcc Shunt Voltage vs. Temperature
14.4 14.2
Graph 6: Overcurrent Threshold Voltage vs. Temperature
136 134
Vcc Shunt Voltage (V)
132
Vcl Voltage (mV)
40 60 80 100
14.0 13.8 13.6 13.4
130 128 126 124 122 120
ICC = 1mA
13.2 -60
-40
-20
0
20
118 -60
-40
-20
0
20
40
60
80
100
Temperature (oC)
Graph 7: Supply Current vs. Shunt Voltage
Temperature (oC)
Graph 8: Vdrop Voltage vs. Temperature 1.00
0.98
60 50 Supply Current (mA)
Vdrop Voltage (V)
40 30 20 10 0 4 6 8 10 12 14 Vshunt (V) 16 18
4
0.96 0.94 0.92 0.90 0.88 0.86 0.84 -60 -40 -20 0 20 40 60 80 100
Temperature (oC)
IXHQ 100PI IXHQ 100SI
Graph 9: Gate Voltage vs. Supply Voltage
16
20 10 0 Attenuation (dB) -10 -20 -30 -40 -50 -60
Graph 10: Typical Noise Attenuation
14
Gate Voltage (V)
12
10
8
6 0 20 40 60 80 100 120
Supply Voltage (V)
-70 1e+1 1e+2 1e+3 1e+4 1e+5 1e+6 Frequency (Hz)
Pin Descriptions
PIN # SYMBOL INV FUNCTION Invert Input DESCRIPTION The invert input controls GSNSin's polarity. When invert input is high compared to AGND, then GSNSin low indicates an insertion/removal event. When invert input is low, then GSNSin high indicates an insertion/removal event. The INV pin controls the polarity sense of this input. A 3uA internal pull-up current source causes logic high when there is no connection at this pin. With INV low or connected to AGND, a GSNSin low (or connected to AGND) will keep RSTout and GATE low, and the external power switch, Q1, off. A disconnected GSNSin pin or when Vcc is applied to it will allow normal operation Positive power-supply voltage input. This pin serves to control the enabling of the shunt circuit. When the pin is high compared to AGND, then the shunt regulator is in off position. A low level at this pin activates the shunt regulator. The output of the power active filter tracks this pin. Adding an external RC network matching the input noise with respect to the 3db point of the filter could reduce the noise to a minimum. This pin sets the drop out MOSFET voltage across the active filter. This input controls the current slope during power up and controls inrush currents. Adding external capacitors to this pin allow regulation and adjustment of the rate of the current slope. The OFFTM pin sets the delay time between powerdown and restart of IXHQ100. Delay time can be increased by adding external capacitors to this pin. The IXHQ100 system zero reference pin.
5
1
15
GSNSin
Ground Sense Input
2 3
VCCin SHNToff
Supply Voltage Shunt Off
4
CAPin
Active lowpass filter capacitor input Active filter offset voltage Slope input
5
VDROP
6
SLOPE
7 8
OFFTM AGND
Off-time Ground
IXHQ 100PI IXHQ 100SI Pin Descriptions (continued)
PIN # SYMBOL FUNCTION DESCRIPTION
9 10
VDDout VCL
Regulator output voltage Overcurrent threshold bias voltage Current input sensor Output Out sensor signal Output Reset N/A
Regulator output voltage provides current to drive the external circuits with respect to AGND. Sets the overcurrent threshold bias voltage.
11 12 13 14 16
SOURCE GATE OUTsns RSTout NC
Input for sensing current through power device with respect to AGND. Control voltage for driving external MOSFET. This signal senses the output voltage of the circuit. A low at this pin indicates detection of an insert/removal event or overcurrent detection. Not Connected
Diagram IXHQ100 Logic Diagram
Figure 2
6
IXHQ 100PI IXHQ 100SI
OPERATION* DEVICE OPERATION*
A hot swap operation involves removal and reinsertion of a device while the system using it remains in operation. Such an operation could cause external capacitors to draw currents high enough to disturb system operations or even cause permanent damage to both the device and the system. The IXHQ100 is designed to prevent any disturbances or damage during such occurrences, allowing the circuit board to be safely inserted and removed from a live backplane. Capable of operating under three modes, the chip also acts as a power active noise filter and an auto-detect circuit.
the external load, Vload, is zero. As VSLOPE rises, its rate of increase determined by the value of the external capacitor, C8 (figure1), and the value of the internal current source, I5. VGATE's rate of increase follows VSLOPE. As soon as VGATE exceeds VthQ1 (figure 1) of the external power MOSFET, drain current IdQ1 starts to flow. The rate of increase of IdQ1 is proportional to the rate of increase of VSLOPE, and is independent of the size of C5 , the total filter capacitance of the load. Note that this rate, which is directly proportional to C7 and inversely proportional to C8, could be adjusted . Similarly the Toff-delay can be adjusted and is directly proportional to the size of C7.
Normal Operation
With continuous -Vin applied, the IXHQ100 acts as an active power filter by modulating the voltage drop across the external Power MOSFET Vds so that any noise on -Vin is cancelled by Vds. The direct connection of IXHQ 100's AGND pin to -Vin allows the Vdrop (internally set to ~750mV) to set the ~90% of the maximum peak noise voltage reject by the IXHQ100. The internal Vdrop setting of ~750 mV allows 1.35 Vpp of noise rejection. Graph on page 5 illustrates the level of ripple attenuation during normal conditions. Notice that the noise rejection is very high (~60db) between 400Hz to 40KHz, which is optimal for most hot swap applications.
Insertion Process Insertion Process
As the circuit board is inserted into the backplane, physical connections should be made to ground to discharge any electrostatic voltage. The insertion process begins when power and ground are supplied to the board through pins on the blackplane. Once power is applied, the IXHQ100 starts up but does not immediately apply power to the output load. The internal Power Up Reset logic (see in Figure 2) turns on for 10 s prior to any other logic. This pulse goes through two NOR gates and resets SRFF1 Flip Flop. Once SRFF1 is reset, the current source, I6, charges the OFFTM pin at a rate proportional to the size of the external capacitor, C7 (fig 1). During the time the OFFTM pin is ramping from 0V to Vrf (~5V), which is the Toff-delay, COMP1 keeps N3 ON so VSLOPE stays at 0V. After Toff-delay, VOFFTMecomes greater than Vrf, and COMP1 goes low, driving N3 to off state. I5 now starts to charge C1, ramping +ve i/p of OA4. OA4 buffers VSLOPE and sets the GATE output ramp. It is assumed that when the circuit board is first inserted into the backplane, the voltage across
Flip-flop setting and resetting
The flip-flop, SRFF1 (fig 2), used in the IXHQ100, is reset dominant. Hence when both S and R inputs are driven high, the SRFF1 remains reset. Under normal operation, S input becomes high whenever OR1 output is high and R input is low. In turn, OR1 goes high if any one of the outputs of EXOR1, or COMP2, or COMP3 goes high. EXOR1 output goes high if it detects the loss of either Gnd or -Vin. If INV input is connected to
*Unless otherwise stated, all symbol and device references are referred to the logic diagram (Fig 2) on page 6
7
IXHQ 100PI IXHQ 100SI Vcc, then GSNSin pin can be used to detect the presence or absence of -Vin. If INV is connected to AGND, then GSNSin pin can be used to detect the presence or absence of Gnd. COMP2 output goes high whenever an overcurrent or a short circuit condition is detected. The inverting input to COMP2 is connected to the VCL output pin which is internally set at approximately 120mV. As shown in Figure 1, one side of R4 is in series with the source of Q1, the drain output of which drives the load connected to J8. The return side of R4 is connected to -Vin through J1. For R4 = 0.02, Q1 source currents greater than 6A will turn on COMP2 and will be considered either an overcurrent or short circuit event. COMP3 goes high whenever the voltage at OUTsns with respect to AGND becomes less than 0.1*VCL(approximately 12mV). This can only occur if either the current drawn by the driven load is less than 600mA (12mV/.02) or -VIN is disconnected. This Auto-Disconnect technique automatically detects load disconnections without needing additional sensors. Thus the SRFF1 will reset when one of the following events occur: 1. Loss of AGND or -Vin. 2. Overcurrent or short circuit. 3. Auto-Disconnection A valid S input into SRFF1 will immediately drive its output, Q1, to high and will turn on both N5 and N4. N5, an open drain output, will result in RSTout being driven low. A current limiting resistor, R1, in series with a 4N35 LED connected to VDD (fig 1) can be used to generate an isolated reset pulse. Turning on N4 will discharge C7 and the internal 10pF capacitor (fig 2). As soon as VOFFTM drops below V =~0.9V, COMP4 in Figure 2 will turn on DROP through NOR1 and NOR2, and resets SRFF1
8
with a high applied to its R input. This act will then turn off both N5 and N4 and allow OFFTM pin to initiate its positive ramp as a result of I6 charging the capacitors C7 (Figure 1) and C2 (Figure 2) connected to the OFFTM pin.
Restart Operation Restart
The IXHQ100 will automatically attempt to restart once a disconnection and reconnection is detected. Either PUR or COMP4 going high will reset SRFF1 during normal operation of the IXHQ100 (fig 2). Resetting SRFF1 turns off N4 and N5, and the OFFTM pin ramps up in response. During this ramp, as long as VOFFTM is less than Vrf=~4.5V, COMP1 will keep N3 on and C1 (Figure 2) and C8 (Figure 1) discharged. After Toff-delay, VOFFTM is at Vrf, COMP1 output then goes low, turning off N3. Now the SLOPE pin is free to ramp up as a result of I5 charging C1 (Figure 2) and C8 (Figure 1). The two unitygain buffers, OA4 and OA5, reflect VSLOPE at the GATE output pin during this positive ramp. As soon as VGATE overcomes the VQ1th, normal operation is resumed.
Fault Operation
When the output load current is such that the voltage drop across the current sense resistor between the SOURCE pin and the AGND exceeds VCL (internally set to ~120 mv), the GATE output is driven low to turn off the external Power MOSFET connected between the load and -Vin. An external capacitor connected between OFFTM pin and AGND pin determines the off time Toff-delay. IXHQ100 will restart the turn on sequence of the external Power MOSFET with a load voltage slope determined by the size of the external capacitor that is connected to the SLOPE pin.
Short Circuit Prevention Short Circuit Prevention
When the IXHQ100 detects a short in the load, a restart is automatically initiated. The GOUT drops to zero and waits one Toff-delay before SLOPE ramps up. As before, normal operation is resumed.
IXHQ 100PI IXHQ 100SI
Package Outlines: 16 PIN TSSOP
Package Outlines: 16 PIN PDIP
Ordering Information
Part Number Package Type IXHQ 100PI IXHQ 100SI 16 PIN PDIP 16 PIN TSSOP Grade Industrial Industrial
IXYS Corporation 3054 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.com
IXYS Semiconducotr GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de
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